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For Information Equipment
MN89201
VGA-NTSC Scan Converter
Overview
The MN89201 converts PC/AT VGA (640 x 480) display data into an NTSC video signal without requiring an external frame memory. It uses filtering to eliminate flicker and produce a high-quality television image.
Note: PC/AT and VGA are registered trademarks of International Business Machines Corporation.
Features
Conversion of PC/AT VGA (640 x 480) display data into NTSC video signal * 8-bit inputs for VGA R, G, and B signals Horizontal frequency: 31.5 kHz Vertical frequency: 59.94 Hz * Conversion of non-interlaced display to interlaced display * Built-in phase-locked loop for synchronizing VGA and NTSC data clocks * Conversion from RGB to YCrCb (4:2:2) format * Data output in NTSC display format (YCrCb24 or YCrCb16-bit) Flicker prevention * Choice of line filters with 3 taps for preventing flicker Processing with only line memory * No need for external VRAM * All processing completes within built-in line memory Choice of readout clocks for NTSC output Choice 1: Choice of clock that has arbitrary frequency and synchronizes with VGA clock External voltage-controlled oscillator in addition to built-in phase-locked loop Choice 2: Choice of clock that has arbitrary frequency and does not synchronize with VGA clock External oscillator Choice 3: Clock with half frequency of the VGA-dot-clock Choose the clock matching the NTSC encoder. The MN89201 offers high-quality NTSC-compatible output from a compact configuration.
Applications
Point-of-sale terminals, Factory automation terminals, word processors, and other terminals
MN89201
Pin Assignment
For Information Equipment
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
VSS VDD YOUT7 YOUT6 YOUT5 YOUT4 YOUT3 YOUT2 VSS VDD YOUT1 YOUT0 CROUT7 CROUT6 CROUT5 CROUT4 VSS VDD CROUT3 CROUT2 CROUT1 CROUT0 CBOUT7 CBOUT6 VSS VDD CBOUT5 CBOUT4 CBOUT3 CBOUT2 CBOUT1 CBOUT0
TEST0 TEST1 TEST2 TEST3 TEST4 BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 GIN0 GIN1 GIN2 GIN3 GIN4 GIN5 GIN6 GIN7 RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 XVSYNCIN XHSYNCIN DOTCLK
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VDD VSS RDCLK XENCRST XBLANK XVSYNC XHSYNC RD2CLK VDD VSS OEON OEOP VDD VSS XOO OSXIN VDD VSS MEMOUT0 MEMOUT1 MEMOUT2 MEMOUT3 MEMOUT4 MEMOUT5 VDD VSS MEMOUT6 MEMOUT7 MODST MODCHAV MODCRCB SXRST
Note: Never leave VDD and VSS pins open.
VSS VDD AEN XRD XWE REGLIN RA3 RA2 RA1 RA0 DB7 DB6 DB5 DB4 VSS VDD DB3 DB2 DB1 DB0 VSS VDD RESET MODSET1 MODSET0 MOD422F MODVFIL MODHFIL MODPIN MINTEST MON1 MON0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(TOP VIEW) QFH128-P-1818
For Information Equipment
Block Diagram
* RDCLK from an external VCO clock synchronized with VGA clock
MN89201
R G B
8 8 8
Latch
RGB-YCrCb converter
Flicker elimination block
Conversion from non-interlaced to interlaced display
8 8 8
Y Cr Cb
DOTCLK XVSYNCIN XHSYNCIN DB[7:0] RA[3:0] CS (AEN) WR RD 8 4 Registers PLL
Control block counters, pulse generator, etc.
Coding interface
1/N
OSC I/F OEOP OEON OSXIN XOO
XVSYNC XHSYNC BLANK RD2CLK RDCLK
lead VCO lag
* RDCLK from VGA clock
R G B
8 8 8
Latch
RGB-YCrCb converter
Flicker elimination block
Conversion from non-interlaced to interlaced display
8 8 8
Y Cr Cb
DOTCLK XVSYNCIN XHSYNCIN DB[7:0] RA[3:0] CS (AEN) WR RD 8 4 Registers PLL
Control block counters, pulse generator, etc.
Coding interface
1/N
OSC I/F
XVSYNC XHSYNC BLANK RD2CLK RDCLK
MN89201
Pin Descriptions
Pin No. 3 Symbol AEN I/O I Chip select signal
For Information Equipment
Function Description "L" level: Register access enabled "H" level: Register access disabled
4 5 6
XRD XWE REGLIN
I I I
Read control signal "L" level: Read enabled Write control signal "L" level: Write enabled Register address mode specification "H" level: Obtain register address from RA[3:0] "L" level: Obtain register address from address register In the latter case, the address of the parameter/mode register are specified by the address register . Address register: 0H (4-bit decode) Data register: 1H (4-bit decode)
7 to 10 11 to 14 17 to 20 23
RA[3:0] DB[7:0] RESET
I I I
Register address specification Host data bus MN89201 reset signal Active "H" This signal initializes internal registers to their default values and resets internal synchronization counters.
24 ,25
MODSET[1:0]
I
Synchronization mode specification pins These specify the RDCLK synchronization mode for output signals to the NTSC encoder (1:0) 0 0: Use an external VCO clock signal synchronized with the VGA clock signal for RDCLK. The XH, XVSYNC, XBLANK, and XENRST signals are generated inside the MN89201 and are outputted. (synchronous) 0 1: Use an external oscillator clock signal not synchronized with the VGA clock signal for RDCLK. The XH and XVSYNC signals are retimed versions of the VGA H and VSYNC signals. (asynchronous) The other outputs use the VGA DOTCLK signal. 1 0: Use the VGA DOTCLK signal for RDCLK. The YCrCb data, XVSYNC, XBLANK, and XENRST signals all are dealt in the VGA clock. An external oscillator is not necessary. (synchronous)
For Information Equipment
Pin Descriptions (continued)
Pin No. 26 Symbol MOD422F I/O I Function Description Cr and Cb output mode specification "L" level: Cr and Cb are both 8 bits (24-bit mode)
MN89201
"H" level: Cr and Cb are multiplexed into 8 bits (16-bit mode) The combined output is sent to CROUT[7:0]. The MODCRCB pin specifies the multiplex order. 27 28 29 MODVFIL MODHFIL MODPIN I I I This pin switches the vertical filter ON and OFF. "L" level: OFF; "H" level: ON This pin switches the horizontal filter ON and OFF. "L" level: OFF; "H" level: ON This pin selects the setting of the filter mode. "H" level: Ignore mode register setting and take filter settings from pins. "L" level: Ignore pins and take filter settings from mode register. 30 31 ,32 33 34 MINTEST MON[1:0] SXRST MODCRCB I I I I Test pin Test pin Keep this pin at "L" level. Keep this pin at "L" level.
This signal resets the synchronization counter only. Active "H" This pin specifies the bit order for multiplexed Cr and Cb output data in the 16-bit mode. "H" level: Cr before Cb "L" level: Cb before Cr
35
MODCHAV
I
This pin selects the default values for the parameter registers determining the vertical position of the television image. "H" level: Use the default setting that centers the PC image in the television display. Setting value is 45 for back porch and 530 for active end. These settings cause one or two PC lines to be lost at both the top and bottom. "L" level: Use the default settings that align the center of the PC image at two or three lines below the center of the television display. Setting value is 35 for back porch and 514 for active end. These settings doesn't lose the tops of the images but cause three or four lines to be lost at the bottom.
MN89201
Pin Descriptions (continued)
Pin No. 36 Symbol MODST I/O I (pin 37).
For Information Equipment
Function Description This pin selects the output signal to the monitor pin, MEMOUT7 "H" level: Pin 37 (normally "H" level) indicates the phase information of VSYNC signal in VGA when the MN89201 is in synchronization. Note: At the time when RESET (pin 23) or SXRST (pin 33) is driven (turned-ON or -OFF), the inner counter of the MN89201 begins to operate in phase with H and VSYNC of VGA. So, the phase shift in VGA after synchronization can cause wrong display. In this case you should survey the phase information in synchronization that is outputted from this pin, and detect the phase variation of the synchronous signal in VGA, then give RESET or SXRST to the MN89201. "L" level: Test signal output.
37
MEMOUT7/ SYNCINF
O
If the MODST pin (pin 36) is "H" level, this pin indicates phase information in synchronization of internal counters and VGA synchronizing signals. If pin 36 is "L" level, this pin is output for a test. Should be left open usually.
38 41 to 46 49 50 53 54 57
MEMOUT [6:0] OSXIN XOO OEOP OEON RD2CLK
O I O O O O
Test pin Normally leave this pin open. External oscillator input pin If an external oscillator is not used, drive this pin at "L" level. External oscillator output pin Internal PLL comparator result signal Internal PLL comparator result signal This data clock is half the frequency of RDCLK, has the same frequency as the clock for Y, Cr, and Cb outputs. The XHSYNC, XVSYNC, and XBLANK signals have a retiming at the rising edge of this clock signal.
58 59 60 61
XHSYNC XVSYNC XBLANK XENRST
O O O O
Horizontal synchronizing output signal (Active "L") Vertical synchronizing output signal (Active "L") Composite blanking output signal (Active "L") Encoder reset signal (Active "L") This signal has four fields interval (when both H and V are at "L" level.) Use it as necessary to control the NTSC encoder.
62
RDCLK
O
Encoder clock Y, Cr, and Cb outputs to the NTSC encoder are synchronized with the rising edge of this clock signal.
For Information Equipment
Pin Descriptions (continued)
Pin No. 65 to 70 73 to 74 75 to 78 81 to 84 85 to 86 89 to 94 97 to 101 102 to 109 110 to 117 118 to 125 126 127 128 TEST[4:0] BIN[7:0] GIN[7:0] RIN[7:0] XVSYNCIN XHSYNCIN DOTCLK I I I I I I I Test pins Keep these pins at "L" level. Blue input signals Green input signals Red input signals Y OUT[7:0] O CR OUT[7:0] O Symbol CB OUT[7:0] I/O O Function Description
MN89201
In the 24-bit mode, color difference output (CB: B-Y). And in the 16-bit mode, CBOUT0 gives the Cr flag: "H" level for Cr output. In the 24-bit mode, color difference output (CR: R-Y). And in the 16-bit mode, these pins yield multiplexed Cr/Cb output. Luminance signal output (Y)
VVGA horizontal synchronizing input signal (Active "L") VGA vertical synchronizing input signal (Active "L") VGA dot clock The chip latches input data from VGA at the rising edge of this clock signal.
Absolute Maximum Ratings
Parameter Power supply voltage Input pin voltage Output pin voltage Output current Output current Power dissipation Operating ambient temperature Storage temperature Symbol VDD VI VO IOL IOH PD Topr Tstg Ratings - 0.3 to +7.0 - 0.3 to VDD+0.3 - 0.3 to VDD+0.3 +12 - 12 1000 - 40 to +70 - 55 to +150 Unit V V V mA mA mW C C
Recommended Operating Conditions
Parameter Power supply voltage Ambient temperature Rise time for input Fall time for input Oscillation frequency Recommended value for external capacitance Symbol VDD Ta tr tf fosc CXI CXO Crystal oscillator 24 MHz VDD=5.0V Built-in feedback resistor Conditions min 4.75 0 0 0 24 12 12 typ 5.0 max 5.25 70 150 150 Unit V C ns ns MHz pF pF
MN89201
Electrical Characteristics
VDD =4.75 to 5.25V, VSS =0.00V, f=25MHz, Ta=0 to 70C Parameter Power supply current during operation Oscillator circuit XOO Built-in feedback resistance "H" level input voltage "L" level input voltage Pull-down resistance Input leakage current Rfb VIH2 VIL2 RPD1 I LIPD VI =VDD, VDD=5.0V VI =VSS VI =VDD or VSS, VDD =5.0V 228 Symbol I DD Conditions VI =VDD or VSS f=25MHz VDD =5.0V Output open min
For Information Equipment
typ
max 126
Unit mA
570
1430 VDD V DD x 0.3
k V V k A
CMOS level input with pull-down resistor: MINTEST VDD x 0.7 0 12 30
75 20
TTL level inputs: RA0 to 3, AEN, BIN0 to 7, GIN0 to 7, MOD422F, RIN0 to 7, XRD, XWE, TEST0 to 4, MODST, DOTCLK, MODPIN, MODSET0 to 1, REGLIN, MODCHAV, MODCRCB, MODHFIL, MODVFIL, XHSYNCIN, XVSYNCIN "H" level input voltage "L" level input voltage Input leakage current Input threshold voltage Hysteresis width Input leakage current VIH1 VIL1 ILI VtHL VtLH Vtt ILI VDD =5.0V VI =VDD or VSS VI =VDD or VSS VDD =4.75 to 5.25V 0.4 0.4 1.8 1.0 0.8 10 V A 2.0 0 VDD 0.8 10 2.4 V V A V
TTL level inputs with Schmidt input: SRST, RESET
Push-pull outputs: RD2CLK, OEON, OEOP, YOUT0 to 7, CBOUT0 to 7, CROUT0 to 7, RDCLK, MEMOUT0 to 7, XBLANK, XHSYNC, XVSYNC, XENRST "H" level output voltage "L" level output voltage Peak output current VOH VOL IO=-4 .0mA VI =VDD or VSS IO=4.0mA VI =VDD or VSS IO (Peak) Absolute maximum rating
(not guaranteed operating value)
VDD- 0.6 0.4 - 12 12
V V mA
CMOS level I/O: DB0 to DB7 "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Output leakage current VIH2 VIL2 VOH VOL ILO IO=-4.0mA VI =VDD or VSS IO=4.0mA VI =VDD or VSS VO=High-impedance state VI =VDD or VSS VO=V DD or VSS Peak output current IO (Peak) Absolute maximum rating
(not guaranteed operating value)
VDD x 0.7 0 VDD -0.6
VDD V DD x 0.3
V V V
0.4 10
V A
-12
12
mA
For Information Equipment
Timing Chart
780 clock cycles
MN89201
640 clock cycles
Active interval (horizontal)
Back porch
Front porch
60 clock cycles Horizontal synchronization Horizontal synchronizing signal 58 clock cycles 118 clock cycles
22 clock cycles Horizontal synchronizing signal
480 lines Active interval (vertical)
Vertical synchronization
Vertical synchronizing signal 2 lines Horizontal synchronizing signal
Vertical synchronizing signal
35 lines
515 lines
525 lines
(for a readout frequency of 12.27 MHz)
MN89201
Application Circuit Example
For Information Equipment
16 SA
Address decoder
AEN
RA0 RA1 RA2 RA3 XRD XWE DB 8 Counters 8 8 8 VGA RIN GIN BIN XVSYNCIN XHSYNCIN DOTCLK 25.175MHz (VGACLK) PLL SEL 1/2nd frequency divider RD2CLK RDCLK CBOUT XHSYNC XVSYNC XENRST YOUT
8 8 8 Y C
MN89201
CROUT
NTSC encoder
RESET
VCO1
OSC
Notes: Choose the clock frequencies to match the synchronization system for the NTSC encoder. The PLL uses the VGA XHSYNCIN (31.5 MHz) clock signal for comparison. The XHSYNC, XVSYNC, and XENRST signals to the NTSC encoder are synchronized with the VGA outputs.
For Information Equipment
Package Dimensions (Unit: mm)
QFH128-P-1818
MN89201
20.00.2 18.00.2 96 97 65 64 (1.25) 33 1 0.5 32 0.20.1 18.00.2 20.00.2 128 (1.25)
1.00.2 3.30.2 3.40.3
0.15-0.05
+0.10
0.10.1
0.1
SEATING PLANE
0.50.2
0 to 10

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